Numerous computerized devices are utilized by consumers throughout the world. In each of these devices, digital data are passed between individual components, often using a shared time-division multiplexed (TDM) bus, either serial and/or parallel, between the components. The data stream on the TDM bus comprises a repeating data cycle or frame, with each data frame being divided into multiple time slots. Each component is granted access to the bus during a certain time slot.
As is well-known in the prior art, the TDM bus typically utilizes an “arbiter” circuit, or master controller, that controls which component has access to the bus at a given time. The conventional master controller assigns the use of the TDM bus to the various components in accordance with a given set of arbitration rules, e.g., a round-robin allocation or an interrupt-driven access resulting in a first come, first served allocation. Flexibility is provided in such conventional devices by allowing the controller to change the duration of the TDM slot, or the number of TDM slots, allocated to any particular component.
Disadvantageously, conventional system bus arbitration can require substantial resources or overhead of the master controller. This is particularly true in multiple processor-based systems, where communication data traffic between the processors increases as requests for access to the arbitrated system bus increase. Moreover, as the size of systems increases and as the number of agents on a particular system bus grows, the arbitration processing becomes enormous. This increased overhead results in a decreased amount of processing available for other tasks. There is thus a need for a more flexible TDM system bus that does not require the significant overhead otherwise conventionally required in a master controller.